In one conventional system, a master apparatus that has received from a slave apparatus, an interrupt signal that is generated only when a particular interrupt event has occurred, executes a corresponding process particular to the interrupt event, without confirming the event causing the interrupt with respect to the slave apparatus (see, for example, Japanese Laid-Open Patent Publication No. 2008-15883). According to one method, an interrupt privilege is sequentially granted to processors and the processor retaining the interrupt privilege performs processing with respect to an interrupt request (see, for example, Japanese Laid-Open Patent Publication No. H6-28321). According to another method, the addresses of multiple processing apparatuses are registered into a register and when an interrupt occurs, the register is referred to and an interrupt is assigned to a relevant processing apparatus (see, for example, Japanese Laid-Open Patent Publication No. S55-85940).
According to a further method, interrupt processing is performed by a processor having the lowest power consumption among processors whose power consumption is within a threshold range (see, for example, Japanese Laid-Open Patent Publication No. 2007-172322). According to still another method, interrupt request signals are ranked according to priority and according to the operation state of a central processing unit (CPU), an interrupt request output signal is input to the CPU, whereby the CPU is caused to execute processing, starting from an interrupt event having a high priority (see, for example, Japanese Laid-Open Patent Publication No. 2000-122963).
According to another method, when the number of events per unit time causing interrupt exceeds a permitted count, no processing is performed for any of the interrupt causing events (see, for example, Japanese Laid-Open Patent Publication No. H10-55282). According to yet another method, when an interrupt occurs, the priority of processors to receive an interrupt request is determined and from the execution level of the processors, whether a processor is to receive an interrupt request is determined (see, for example, Japanese Laid-Open Patent Publication No. H4-178869).
Nonetheless, with the conventional methods, when an interrupt request occurs, the CPU immediately suspends processing a thread under execution and performs interrupt processing. Therefore, when the load of the CPU is large and interrupt processing occurs frequently, problems arise such as delays in the processing of the user application and situations where user performance drops consequent to interrupt processing related to user performance of the user application not being implemented.
Examples of user performance include the time consumed to respond to a key strike on a keyboard used as an input apparatus of an electronic computer, the response of a touch panel when a touch panel is used, the time consumed to download data, etc. A further example of user performance is performance related to signal detection for an application performing wireless communication when the electronic computer performs wireless communication.